Open opportunities
Physical Design Engineer
About The Position
We are looking for an experienced ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What You’ll Do
- Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
- Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
- Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
- Support field teams on complex technical issues when needed.
Requirements
- 3-5 years of hands-on experience with ASIC physical design (RTL-to-GDS).
- Proven experience taking multiple full-chip SoCs from RTL through tapeout.
- Deep knowledge of Cadence and/or Synopsys backend flows (experience with both is a strong plus).
- Strong understanding of PnR, timing closure, SI, power, DRC/LVS, and signoff.
- Excellent debugging and problem-solving skills.
- Strong scripting skills in TCL and Python.
Nice-to-have / Advantage
- Experience with multiple power domains and low-power design techniques.
- Background that spans both frontend (RTL) and backend.
- Experience influencing or defining methodology across teams or projects.